Read e-book online 1364.1-2002 IEEE Standard for Verilog Register Transfer PDF

ISBN-10: 0738135011

ISBN-13: 9780738135014

Typical syntax and semantics for VerilogR HDL-based RTL synthesis are defined during this ordinary.

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Extra resources for 1364.1-2002 IEEE Standard for Verilog Register Transfer Level Synthesis

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1 Task declarations task_declaration ::= task [ automatic ] task_identifier ; { task_item_declaration } statement endtask | task [ automatic ] task_identifier ( task_port_list ) ; { block_item_declaration } statement endtask 52 Copyright © 2002 IEEE. All rights reserved. 1-2002 task_item_declaration ::= block_item_declaration | { attribute_instance } tf_input_declaration ; | { attribute_instance } tf_output_declaration ; | { attribute_instance } tf_inout_declaration ; task_port_list ::= task_port_item { , task_port_item } task_port_item ::= { attribute_instance } tf_input_declaration | { attribute_instance } tf_output_declaration | { attribute_instance } tf_inout_declaration tf_input_declaration ::= input [ reg ] [ signed ] [ range ] list_of_port_identifiers | input [ task_port_type ] list_of_port_identifiers tf_output_declaration ::= output [ reg ] [ signed ] [ range ] list_of_port_identifiers | output [ task_port_type ] list_of_port_identifiers tf_inout_declaration ::= inout [ reg ] [ signed ] [ range ] list_of_port_identifiers | inout [ task_port_type ] list_of_port_identifiers task_port_type ::= time | real | realtime | integer block_item_declaration ::= { attribute_instance } block_reg_declaration | { attribute_instance } event_declaration | { attribute_instance } integer_declaration | { attribute_instance } local_parameter_declaration | { attribute_instance } parameter_declaration ; | { attribute_instance } real_declaration | { attribute_instance } realtime_declaration | { attribute_instance } time_declaration block_reg_declaration ::= reg [ signed ] [ range ] list_of_block_variable_identifiers ; list_of_block_variable_identifiers ::= block_variable_type { , block_variable_type } block_variable_type ::= variable_identifier | variable_identifier dimension { dimension } Use of variables (both reading the value of and writing a value to) that are defined outside a task declaration but within the enclosing module declaration shall be supported.

Probe_port = PROBE_PORT *) // Bring to a test port. wire [WIDTH-1:0] qbar; // Test point. assign qbar = ~q; // Equation for test point. always @(posedge clk or posedge rst) 26 Copyright © 2002 IEEE. All rights reserved. PROBE_PORT (1)) ff #(WIDTH_ONE, PROBE_PORT_ON) // Bring probe port out. PROBE_PORT (0)) ff #(WIDTH_ONE, PROBE_PORT_OFF) // Do NOT bring probe port out. rst (rst)); endmodule // top NOTES 1—This attribute is needed for the verification of gate-level model designs at the “grey-box” level where internal signals may be needed for triggering of events in a verifier (example, the occurrence of a simulation push/pop of a fifo).

7 Intra-assignment timing controls blocking_assignment ::= variable_lvalue = [ delay_or_event_control ] expression nonblocking_assignment ::= variable_lvalue <= [ delay_or_event_control ] expression 50 Copyright © 2002 IEEE. All rights reserved. 1-2002 delay_control ::= # delay_value | # ( mintypmax_expression ) delay_or_event_control ::= delay_control | event_control | repeat ( expression ) event_control event_control ::= @ event_identifier | @ ( event_expression ) |@* |@(*) The event control, including the implicit form, shall only be supported at the topmost statement in an always construct.

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1364.1-2002 IEEE Standard for Verilog Register Transfer Level Synthesis


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